Field
This disclosure relates generally to testing of integrated circuits, and more specifically, to storage elements used in scan testing.
Related Art
Today many integrated circuits incorporate design for test (DFT) techniques such as scan testing. Scan testing features can include a collection of flip-flops interconnected in the form of a scan chain. To minimize test time of complex integrated circuits, several short scan chains can be configured in parallel rather than using one long scan chain. In a scan test mode, each scan chain can be configured as a single shift register with a common clock. In this configuration, a scan controller can synchronously shift test data through each scan chain simultaneously. The resulting power consumption during a scan test mode therefore can be significantly larger than during a functional operation mode. To accommodate large scan test mode power consumption, the size of power grids is increased, which consequently increases overall die area and product costs.